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85314bgi-01 www.icst.com/products/hiperclocks.html rev. e august 1, 2007 1 ics85314i-01 l ow s kew , 1- to -5 d ifferential - to -2.5v/3.3v lvpecl f anout b uffer g eneral d escription the ics85314i-01 is a low skew, high perfor- mance 1-to-5 differential-to-2.5v/3.3v lvpecl fanout buffer and a member of the hiperclocks? family of high performance clock solutions from ics. the ics85314i-01 has two selectable clock inputs. the clk0, nclk0 pair can accept most standard differential input levels. the single-ended clk1 can accept lvcmos or lvttl input levels. the clock enable is internally synchronized to eliminate runt clock pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin. guaranteed output and part-to-part skew characteristics make the ics85314i-01 ideal for those applications demand- ing well defined performance and repeatability. f eatures ? 5 differential 2.5v/3.3v lvpecl outputs ? selectable differential clk0, nclk0 or lvcmos inputs ? clk0, nclk0 pair can accept the following differential input levels: lvpecl, lvds, lvhstl, hcsl, sstl ? clk1 can accept the following input levels: lvcmos or lvttl ? maximum output frequency: 700mhz ? translates any single-ended input signal to 3.3v lvpecl levels with resistor bias on nclk input ? output skew: 30ps (maximum), tssop package 50ps (maximum), soic package ? part-to-part skew: 350ps (maximum) ? propagation delay: 1.8ns (maximum) ? rms phase jitter @ 155.52mhz (12khz - 20mhz): 0.05ps (typical) ? lvpecl mode operating voltage supply range: v cc = 2.375v to 3.8v, v ee = 0v ? -40c to 85c ambient operating temperature ? available in both standard and lead-free rohs-compliant packages b lock d iagram p in a ssignment q0 nq0 q1 nq1 q2 nq2 q3 nq3 q4 nq4 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 v cc nclk_en v cc nc clk1 clk0 nclk0 nc clk_sel v ee hiperclocks? ics ics85314i-01 20-lead tssop 6.5mm x 4.4mm x 0.92mm package body g package top view ics85314i-01 20-lead soic 7.5mm x 12.8mm x 2.3mm package body m package top view clk0 nclk0 clk1 q0 nq0 q1 nq1 q2 nq2 q3 nq3 q4 nq4 0 1 nclk_en clk_sel d q le 0 1
85314bgi-01 www.icst.com/products/hiperclocks.html rev. e august 1, 2007 2 ics85314i-01 l ow s kew , 1- to -5 d ifferential - to -2.5v/3.3v lvpecl f anout b uffer t able 1. p in d escriptions t able 2. p in c haracteristics lobmy sr etemara ps noitidnoctse tm umini ml acipy tm umixa ms tinu c ni ecnaticapactupni 4f p r pullup rotsiserpulluptupni 1 5k r nwodllup rotsisernwodlluptupni 1 5k rebmu ne ma ne py tn oitpircsed 2, 10 qn,0 qt uptu o. slevelecafretnilcepvl.riaptuptuolaitnereffid 4, 31 qn,1 qt uptu o. slevelecafretnilcepvl.riaptuptuolaitnereffid 6, 52 qn,2 qt uptu o. slevelecafretnilcepvl.riaptuptuolaitnereffid 8, 73 qn,3 qt uptu o. slevelecafretnilcepvl.riaptuptuolaitnereffid 01, 94 qn,4 qt uptu o. slevelecafretnilcepvl.riaptuptuolaitnereffid 1 1v ee rewo p. nipylppusevitagen 2 1l es_kl ct upn in wodllup .tupni1klcstceles,hgihnehw.tupnitceleskcolc .stupni0klcn,0klcstceles,wolnehw .slevelecafretnisomcvl/lttvl 71,3 1c nd esun u. tcennocon 4 10 klc nt upn ip ullu p. tupnikcolclaitnereffidgnitrevni 5 10 kl ct upn in wodllu p. tupnikcolclaitnereffidgnitrevni-non 6 11 kl ct upn in wodllu p. slevelecafretnisomcvl/lttvl.tupnikcolc 02,8 1v cc rewo p. snipylppusevitisop 9 1n e_klc nt upn in wodllup kcolcwollofstuptuokcolc,wolnehw.elbanekcolcgnizinorhcnys decroferastuptuoqn,woldecroferastuptuoq,hgihnehw.tupni .slevelecafretnisomcvl/lttvl.hgih :eton pullup dna nwodllup .seulavlacipytrof,scitsiretcarahcnip,2elbatees.srotsisertupnilanretniotrefer
85314bgi-01 www.icst.com/products/hiperclocks.html rev. e august 1, 2007 3 ics85314i-01 l ow s kew , 1- to -5 d ifferential - to -2.5v/3.3v lvpecl f anout b uffer t able 3a. c ontrol i nput f unction t able t able 3b. c lock i nput f unction t able stupn is tuptuo ne_klc nl es_kl ce cruosdetcele s4 q:0 q4 qn:0qn 00 0 klcn,0kl cd elban ed elbane 01 1 kl cd elban ed elbane 10 0 klcn,0kl cw ol;delbasi dh gih;delbasid 11 1 kl cw ol;delbasi dh gih;delbasid egdekcolctupnignillafagniwollofdelbanerodelbasiderastuptuokcolceht,sehctiwsne_klcnretfa .1erugifninwohssa stupni1klcdna0klcn,0klcehtfonoitcnufaerastuptuoehtfoetatseht,edomevitcaehtni .b3elbatnidebircsedsa stupn is tuptuo edomtuptuoottupn iy tiralop 1klcro0kl c0 klc n4 q:0 q4 qn:0qn 01w o lh gi hl aitnereffidotlaitnereffi dg nitrevninon 10 h gi hw o ll aitnereffidotlaitnereffi dg nitrevninon f igure 1. nclk_en t iming d iagram enabled disabled nclk0 clk0, clk1 nclk_en nq0:nq4 q0:q4
85314bgi-01 www.icst.com/products/hiperclocks.html rev. e august 1, 2007 4 ics85314i-01 l ow s kew , 1- to -5 d ifferential - to -2.5v/3.3v lvpecl f anout b uffer t able 4a. p ower s upply dc c haracteristics , v cc = 2.375v to 3.8v, v ee = 0v, t a = -40c to 85c t able 4b. lvcmos / lvttl dc c haracteristics , v cc = 2.375v to 3.8v, v ee = 0v, t a = -40c to 85c lobmy sr etemara ps noitidnoctse tm umini ml acipy tm umixa ms tinu v hi egatlovhgihtupni les_klc,ne_klc n2 v cc 3.0 +v 1kl c2 v cc 3.0 +v v li egatlovwoltupni les_klc,ne_klc n3 .0 -8 . 0v 1kl c3 .0 -3 . 1v i hi tnerruchgihtupni ,1klc ne_klcn,les_klc v ni v= cc v8.3 =0 5 1a i li tnerrucwoltupni ,1klc ne_klcn,les_klc v cc v,v8.3= ni v0 =5 -a lobmy sr etemara ps noitidnoctse tm umini ml acipy tm umixa ms tinu v cc egatlovylppusrewo p5 73. 23 . 38 . 3v i ee tnerrucylppusrewop 0 8a m t able 4c. d ifferential dc c haracteristics , v cc = 2.375v to 3.8v, v ee = 0v, t a = -40c to 85c lobmy sr etemara ps noitidnoctse tm umini ml acipy tm umixa ms tinu i hi tnerruchgihtupni 0klc nv cc v= ni v8.3 =5 a 0kl cv cc v= ni v8.3 =0 5 1a i li tnerrucwoltupni 0klc nv cc v,v8.3= ni v0 =0 51 -a 0kl cv cc v,v8.3= ni v0 =5 -a v pp egatlovtupnikaep-ot-kaep 51. 03 . 1v v rmc ;egatlovtupniedomnommoc 2,1eton 5. 0v cc 58.0 -v vsi0klcn,0klcrofegatlovtupnimumixamehtsnoitacilppadedneelgnisrof:1eton cc .v3.0+ vsadenifedsiegatlovedomnommoc:2eton hi . a bsolute m aximum r atings supply voltage, v cc 4.6v inputs, v i -0.5v to v cc + 0.5v outputs, i o continuous current 50ma surge current 100ma package thermal impedance, ja 20 lead tssop 73.2c/w (0 lfpm) 20 lead soic 46.2c/w (0 lfpm) storage temperature, t stg -65c to 150c note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only. functional operation of product at these conditions or any conditions be- yond those listed in the dc characteristics or ac character- istics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability.
85314bgi-01 www.icst.com/products/hiperclocks.html rev. e august 1, 2007 5 ics85314i-01 l ow s kew , 1- to -5 d ifferential - to -2.5v/3.3v lvpecl f anout b uffer t able 4d. lvpecl dc c haracteristics , v cc = 2.375v to 3.8v, v ee = 0v, t a = -40c to 85c t able 5. ac c haracteristics , v cc = 2.375v to 3.8v, v ee = 0v, t a = -40c to 85c lobmy sr etemara ps noitidnoctse tm umini ml acipy tm umixa ms tinu f xam ycneuqerftuptuo 0klcn,0klc 00 7z hm 1klc 00 3z hm )?(tij t5 eton;)modnar(rettijesahpsmr :egnarnoitargetni )zhm02-zhk2 1( 50. 0s p pt hl 1eton;hgihotwol,yalednoitagaporp 0. 14 . 18 . 1s n t )o(ks ;wekstuptuo 6,3eton egakcapposst 0 3s p egakcapcios 0 5s p t )pp(k s6 ,4eton;wekstrap-ot-trap 05 3s p t r t/ f emitllaf/esirtuptu o% 08ot%0 20 0 20 0 7s p cd oe lcycytudtuptuo 0klcn,0kl c? zhm00 75 45 5% 1kl c? zhm05 25 45 5% ftaderusaemsretemaraplla xam .esiwrehtodetonsselnu rettijddatonseodtrapeht.tuptuoehtnorettijehtlauqelliwtupniehtnorettijelcyc-ot-elcyceht .tniopgnissorctuptuolaitnereffidehtottniopgnissorctupnilaitnereffidehtmorfderusaem:1eton vmorfderusaem:2eton cc .tniopgnissorctuptuolaitnereffidehtottniopgnissorctupni2/ .snoitidnocdaollauqehtiwdnaegatlovylppusemasehttastuptuoneewtebwekssadenifed:3eton .stniopssorclaitnereffidtuptuoehttaderusaem segatlovylppusemasehttagnitareposecivedtnereffidnostuptuoneewtebwekssadenifed:4eton derusaemerastuptuoeht,ecivedhcaenostupnifoepytemasehtgnisu.snoitidnocdaollauqehtiwdna .stniopssorclaitnereffidehtta .tolpesionesahpehtotreferesaelp:5eton .56dradnatscedejhtiwecnadroccanidenifedsiretemarapsiht:6eton lobmy sr etemara ps noitidnoctse tm umini ml acipy tm umixa ms tinu v ho 1eton;egatlovhgihtuptu ov cc 4.1 -v cc 9.0 -v v lo 1eton;egatlovwoltuptu ov cc 0.2 -v cc 7.1 -v v gniws gniwsegatlovtuptuokaep-ot-kaep 6. 00 . 1v 05htiwdetanimretstuptuo:1eton vot cc .v2-
85314bgi-01 www.icst.com/products/hiperclocks.html rev. e august 1, 2007 6 ics85314i-01 l ow s kew , 1- to -5 d ifferential - to -2.5v/3.3v lvpecl f anout b uffer t ypical p hase n oise at 155.52mh z 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 1k 10k 100k 1m 10m 100m 155.52mhz rms phase jitter (random) 12khz to 20mhz = 0.05ps (typical) o ffset f requency (h z ) n oise p ower dbc hz raw phase noise data ?
85314bgi-01 www.icst.com/products/hiperclocks.html rev. e august 1, 2007 7 ics85314i-01 l ow s kew , 1- to -5 d ifferential - to -2.5v/3.3v lvpecl f anout b uffer p arameter m easurement i nformation d ifferential i nput l evel 3.3v o utput l oad ac t est c ircuit scope qx nqx lvpecl 2v -1.8v -0.375v v cmr cross points v pp v cc v ee clk0 nclk0 v cc v ee p art - to -p art s kew t sk(o) nqx qx nqy qy o utput s kew rms p hase j itter phase noise mas k offset frequency f 1 f 2 phase noise plot rms jitter = area under the masked phase noise plot noise power o utput d uty c ycle /p ulse w idth /p eriod t pw t period t pw t period odc = x 100% q0:q4 nq0:nq4 t sk(o) qx qy part 1 part 2 nqx nqy
85314bgi-01 www.icst.com/products/hiperclocks.html rev. e august 1, 2007 8 ics85314i-01 l ow s kew , 1- to -5 d ifferential - to -2.5v/3.3v lvpecl f anout b uffer t pd p ropagation d elay (d ifferential i nput ) o utput r ise /f all t ime clock outputs 20% 80% 80% 20% t r t f v sw i n g clk0 nclk0 q0:q4 nq0:nq4 p ropagation d elay (lvcmos i nput ) t pd clk1 q0:q4 nq0:nq4
85314bgi-01 www.icst.com/products/hiperclocks.html rev. e august 1, 2007 9 ics85314i-01 l ow s kew , 1- to -5 d ifferential - to -2.5v/3.3v lvpecl f anout b uffer a pplication i nformation f igure 2. s ingle e nded s ignal d riving d ifferential i nput figure 2 shows how the differential input can be wired to accept single ended levels. the reference voltage v_ref = v cc /2 is generated by the bias resistors r1, r2 and c1. this bias circuit should be located as close as possible to the input pin. the ratio w iring the d ifferential i nput to a ccept s ingle e nded l evels of r1 and r2 might need to be adjusted to position the v_ref in the center of the input voltage swing. for example, if the input clock swing is only 2.5v and v cc = 3.3v, v_ref should be 1.25v and r2/r1 = 0.609. v_ref r1 1k c1 0.1u r2 1k single ended clock input clk nclk vcc i nputs : clk i nput : for applications not requiring the use of a clock input, it can be left floating. though not required, but for additional protection, a 1k resistor can be tied from the clk input to ground. clk/nclk i nput : for applications not requiring the use of the differential input, both clk and nclk can be left floating. though not required, but for additional protection, a 1k resistor can be tied from clk to ground. lvcmos c ontrol p ins : all control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. a 1k resistor can be used. r ecommendations for u nused i nput and o utput p ins o utputs : lvpecl o utput all unused lvpecl outputs can be left floating. we recommend that there is no trace attached. both sides of the differential output pair should either be left floating or terminated.
85314bgi-01 www.icst.com/products/hiperclocks.html rev. e august 1, 2007 10 ics85314i-01 l ow s kew , 1- to -5 d ifferential - to -2.5v/3.3v lvpecl f anout b uffer f igure 3c. h i p er c lock s clk/ n clk i nput d riven by 3.3v lvpecl d river f igure 3b. h i p er c lock s clk/ n clk i nput d riven by 3.3v lvpecl d river f igure 3d. h i p er c lock s clk/ n clk i nput d riven by 3.3v lvds d river 3.3v r1 50 r3 50 zo = 50 ohm lvpecl zo = 50 ohm hiperclocks clk nclk 3.3v input r2 50 zo = 50 ohm input hiperclocks clk nclk 3.3v r3 125 r2 84 zo = 50 ohm 3.3v r4 125 lvpecl r1 84 3.3v d ifferential c lock i nput i nterface the clk /nclk accepts lvds, lvpecl, lvhstl, sstl, hcsl and other differential signals. both v swing and v oh must meet the v pp and v cmr input requirements. figures 3a to 3e show inter- face examples for the hiperclocks clk/nclk input driven by the most common driver types. the input interfaces suggested f igure 3a. h i p er c lock s clk/ n clk i nput d riven by ics h i p er c lock s lvhstl d river here are examples only. please consult with the vendor of the driver component to confirm the driver termination requirements. for example in figure 3a, the input termination applies for ics hiperclocks lvhstl drivers. if you are using an lvhstl driver from another vendor, use their termination recommendation. 1.8v r2 50 input lvhstl driver ics hiperclocks r1 50 lvhstl 3.3v zo = 50 ohm zo = 50 ohm hiperclocks clk nclk f igure 3e. h i p er c lock s clk/ n clk i nput d riven by 3.3v lvpecl d river with ac c ouple zo = 50 ohm r3 125 hiperclocks clk nclk 3.3v r5 100 - 200 3.3v r2 84 3.3v r6 100 - 200 input r5,r6 locate near the driver pin. zo = 50 ohm r1 84 r4 125 c2 lvpecl c1 zo = 50 ohm r1 100 3.3v lvds_driv er zo = 50 ohm receiv er clk nclk 3.3v
85314bgi-01 www.icst.com/products/hiperclocks.html rev. e august 1, 2007 11 ics85314i-01 l ow s kew , 1- to -5 d ifferential - to -2.5v/3.3v lvpecl f anout b uffer the clock layout topology shown below is a typical termina- tion for lvpecl outputs. the two different layouts mentioned are recommended only as guidelines. fout and nfout are low impedance follower outputs that gen- erate ecl/lvpecl compatible outputs. therefore, terminating resistors (dc current path to ground) or current sources must be used for functionality. these outputs are designed to drive v cc - 2v 50 50 rtt z o = 50 z o = 50 fout fin rtt = z o 1 ((v oh + v ol ) / (v cc ? 2)) ? 2 3.3v 125 125 84 84 z o = 50 z o = 50 fout fin 50 transmission lines. matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. figures 4a and 4b show two different layouts which are recommended only as guidelines. other suitable clock lay- outs may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. f igure 4b. lvpecl o utput t ermination f igure 4a. lvpecl o utput t ermination t ermination for 3.3v lvpecl o utputs
85314bgi-01 www.icst.com/products/hiperclocks.html rev. e august 1, 2007 12 ics85314i-01 l ow s kew , 1- to -5 d ifferential - to -2.5v/3.3v lvpecl f anout b uffer t ermination for 2.5v lvpecl o utput figure 5a and figure 5b show examples of termination for 2.5v lvpecl driver. these terminations are equivalent to ter- minating 50 to v cc - 2v. for v cc = 2.5v, the v cc - 2v is very close to ground level. the r3 in figure 5b can be eliminated and the termination is shown in figure 5c. f igure 5c. 2.5v lvpecl t ermination e xample f igure 5b. 2.5v lvpecl d river t ermination e xample f igure 5a. 2.5v lvpecl d river t ermination e xample r2 62.5 zo = 50 ohm r1 250 + - 2.5v 2,5v lvpecl driv er r4 62.5 r3 250 zo = 50 ohm 2.5v vcc=2.5v r1 50 r3 18 zo = 50 ohm zo = 50 ohm + - 2,5v lvpecl driv er vcc=2.5v 2.5v r2 50 2,5v lvpecl driv er vcc=2.5v r1 50 r2 50 2.5v zo = 50 ohm zo = 50 ohm + -
85314bgi-01 www.icst.com/products/hiperclocks.html rev. e august 1, 2007 13 ics85314i-01 l ow s kew , 1- to -5 d ifferential - to -2.5v/3.3v lvpecl f anout b uffer p ower c onsiderations this section provides information on power dissipation and junction temperature for the ics85314i-01. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the ics85314i-01 is the sum of the core power plus the power dissipated in the load(s). the following is the power dissipation for v cc = 3.8v, which gives worst case results. note: please refer to section 3 for details on calculating power dissipated in the load. ? power (core) max = v cc_max * i ee_max = 3.8v * 80ma = 304mw ? power (outputs) max = 30.2mw/loaded output pair if all outputs are loaded, the total power is 5 * 30.2mw = 151mw total power _max (3.465v, with all outputs switching) = 304mw + 151mw = 455mw 2. junction temperature. junction temperature, tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. the maximum recommended junction temperature for hiperclocks tm devices is 125c. the equation for tj is as follows: tj = ja * pd_total + t a tj = junction temperature ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ja must be used. assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6c/w per table 6a below. therefore, tj for an ambient temperature of 85c with all outputs switching is: 85c + 0.455w * 66.6c/w = 115c. this is well below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow , and the type of board (single layer or multi-layer). ? ? ja by velocity (linear feet per minute) 0 200 500 single-layer pcb, jedec standard test boards 114.5c/w 98.0c/w 88.0c/w multi-layer pcb, jedec standard test boards 73. 2c/w 66.6c/w 63.5c/w note: most modern pcb designs use multi-layered boards. the data in the second row pertains to most designs. t able 6a. t hermal r esistance ? ? ja for 20- pin tssop, f orced c onvection ? ? ja by velocity (linear feet per minute) 0 200 500 single-layer pcb, jedec standard test boards 83. 2c/w 65.7c/w 57.5c/w multi-layer pcb, jedec standard test boards 46. 2c/w 39.7c/w 36.8c/w note: most modern pcb designs use multi-layered boards. the data in the second row pertains to most designs. t able 6b. t hermal r esistance ? ? ja for 20- pin soic, f orced c onvection
85314bgi-01 www.icst.com/products/hiperclocks.html rev. e august 1, 2007 14 ics85314i-01 l ow s kew , 1- to -5 d ifferential - to -2.5v/3.3v lvpecl f anout b uffer 3. calculations and equations. lvpecl output driver circuit and termination are shown in figure 6. t o calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of v cc - 2v. ? for logic high, v out = v oh_max = v cc_max ? 1.0v (v cc_max - v oh_max ) = 1.0v ? for logic low, v out = v ol_max = v cc_max ? 1.7v (v cc_max - v ol_max ) = 1.7v pd_h is power dissipation when the output drives high. pd_l is the power dissipation when the output drives low. pd_h = [(v oh_max ? (v cc_max - 2v))/r l ] * (v cc_max - v oh_max ) = [(2v - (v cc_max - v oh_max )) /r l ] * (v cc_max - v oh_max ) = [(2v - 1v)/50 ] * 1v = 20.0mw pd_l = [(v ol_max ? (v cc_max - 2v))/r l ] * (v cc_max - v ol_max ) = [(2v - (v cc_max - v ol_max )) /r l ] * (v cc_max - v ol_max ) = [(2v - 1.7v)/50 ] * 1.7v = 10.2mw total power dissipation per output pair = pd_h + pd_l = 30.2mw f igure 6. lvpecl d river c ircuit and t ermination q1 v out v cc rl 50 v cc - 2v
85314bgi-01 www.icst.com/products/hiperclocks.html rev. e august 1, 2007 15 ics85314i-01 l ow s kew , 1- to -5 d ifferential - to -2.5v/3.3v lvpecl f anout b uffer r eliability i nformation t ransistor c ount the transistor count for ics85314i-01 is: 674 compatible to part number mc100lvel14 t able 7a. ja vs . a ir f low t able for 20 l ead tssop ? ? ja by velocity (linear feet per minute) 0 200 500 single-layer pcb, jedec standard test boards 114.5c/w 98.0c/w 88.0c/w multi-layer pcb, jedec standard test boards 73. 2c/w 66.6c/w 63.5c/w note: most modern pcb designs use multi-layered boards. the data in the second row pertains to most designs. 0 200 500 single-layer pcb, jedec standard test boards 83. 2c/w 65.7c/w 57.5c/w multi-layer pcb, jedec standard test boards 46. 2c/w 39.7c/w 36.8c/w note: most modern pcb designs use multi-layered boards. the data in the second row pertains to most designs. t able 7b. ja vs . a ir f low t able for 20 l ead soic ? ? ja by velocity (linear feet per minute)
85314bgi-01 www.icst.com/products/hiperclocks.html rev. e august 1, 2007 16 ics85314i-01 l ow s kew , 1- to -5 d ifferential - to -2.5v/3.3v lvpecl f anout b uffer p ackage o utline - g s uffix for 20 l ead tssop t able 8a. p ackage d imensions reference document: jedec publication 95, mo-153 lobmys sretemillim mumini mm umixam n0 2 a- -0 2.1 1 a5 0. 05 1.0 2 a0 8. 05 0.1 b9 1. 00 3.0 c9 0. 00 2.0 d0 4. 60 6.6 ec isab04.6 1 e0 3. 40 5.4 ec isab56.0 l5 4. 05 7.0 0 8 aa a- -0 1.0
85314bgi-01 www.icst.com/products/hiperclocks.html rev. e august 1, 2007 17 ics85314i-01 l ow s kew , 1- to -5 d ifferential - to -2.5v/3.3v lvpecl f anout b uffer p ackage o utline - m s uffix for 20 l ead soic t able 8b. p ackage d imensions reference document: jedec publication 95, ms-013, mo-119 lobmys sretemillim mumini mm umixam n0 2 a- -5 6.2 1 a0 1. 0- - 2 a5 0. 25 5.2 b3 3. 01 5.0 c8 1. 02 3.0 d0 6.2 10 0.31 e0 4. 70 6.7 ec isab72.1 h0 0.0 15 6.01 h5 2 . 05 7.0 l0 4. 07 2.1 0 8
85314bgi-01 www.icst.com/products/hiperclocks.html rev. e august 1, 2007 18 ics85314i-01 l ow s kew , 1- to -5 d ifferential - to -2.5v/3.3v lvpecl f anout b uffer t able 9. o rdering i nformation while the information presented herein has been checked for both accuracy and reliability, integrated circuit systems, incorpor ated (ics) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patents, or licenses are implied. this product is intended for use in normal commercial and industrial applications. any other applications such as those requiring high reliability, or other ext raordinary environmental requirements are not recommended without additional processing by ics. ics reserves the right to change any circuitry or specifications without notice. ics does not authorize or warrant any ics product for use in life support devices or critical medical instruments. the aforementioned trademark, hiperclocks is a trademark of integrated circuit systems, inc. or its subsidiaries in the united states and/or other countries. note: parts that are ordered with an ?lf? suffix to the part number are the pb-free configuration and are rohs compliant. rebmunredro/tra pg nikra me gakca pg nigakcapgnippih se rutarepmet 10-igb41358sc i1 0ib41358sc ip osstdael0 2e bu tc 58otc04- t10-igb41358sc i1 0ib41358sc ip osstdael0 2l eer&epat005 2c 58otc04- fl10-igb41358sc il 10ib4135sc ip osst"eerf-dael"dael0 2e bu tc 58otc04- tfl10-igb41358sc il 10ib4135sc ip osst"eerf-dael"dael0 2l eer&epat005 2c 58otc04- 10-imb41358sc i1 0-ib41358sc ic iosdael0 2e bu tc 58otc04- t10-imb41358sc i1 0-ib41358sc ic iosdael0 2l eer&epat000 1c 58otc04- fl10-imb41358sc if l10-imb41358sc ic ios"eerf-dael"dael0 2e bu tc 58otc04- tfl10-imb41358sc if l10-imb41358sc ic ios"eerf-dael"dael0 2l eer&epat000 1c 58otc04-
85314bgi-01 www.icst.com/products/hiperclocks.html rev. e august 1, 2007 19 ics85314i-01 l ow s kew , 1- to -5 d ifferential - to -2.5v/3.3v lvpecl f anout b uffer teehsyrotsihnoisiver ve re lba te ga pe gnahcfonoitpircse de tad a 7 8 9 51 .margaidlangisdedneelgnis,2erugifdetadpu .noi tces"stuptuolcepvlv5.2rofnoitanimret"dedda .noitces"ecafretnitupnilaitnereffid"dedda .b.verota.vermorfgnikramdnarebmunredrodetcerroc 30/13/3 b 2t 5t 1 2 5 6 8 9 .noitcesserutaefottellubesionesahpdedda cdegnahc ni .lacipytfp4ot.xamfp4morf .rettijesahpsmrdedda-elbatscitsiretcarahcca .tolprettijesahpdedda .smargaidtuptuolcepvlv3.3rofnoitanimretdetadpu .noitcestuptuolcepvlv5.2rofnoitanimretdetadpu 40/11/8 c 5t 1 4 5 7 .wekstupt uoegakcapciosdedda-noitcesserutaef .ecnadepmilamrehtegakcapciosdedda-sgnitarmumixametulosba .wekstuptuorofegakcapciosdedda-elbatscitsiretcarahcca smrdnawekstrap-ot-trapdedda-noitamrofnitnemerusaemretemarap .smargaidrettijesahp 50/22/3 d 5t 1 5 .xamsp053ot.xamsp052morfwekstrap-ot-trapdegnahc-noitcesserutaef ot.xamsp052morfwekstrap-ot-trapdegnahc-elbatscitsiretcarahcca .xamsp053 50/42/5 e d4t 9t 5 9 81 vdegnahc-elbatscitsiretcarahccdlcepvl ho vmorfxam cc otv0.1- v cc .v9.0- dedda-noitcesnoitamrofninoitacilppa tupnidesunurofsnoitadnemmocer .sniptuptuodna .rebmuntrapeerf-daelposstdedda 50/32/9 e9 t8 1g nikrameerfdaeldedda-elbatnoitamrofnigniredro 70/1/8

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